Embedded Dynamic Memory and Charge-Mode Logic for Parallel Array Processing
نویسندگان
چکیده
We present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 128 vector-matrix multiplier on a single 3 mm 3 mm chip fabricated in standard CMOS 0.5 m technology achieves 8-bit effective resolution, dissipates 0.5 pJ per multiply-accumulate and offers 2 10 binary MACS (multiply accumulates per second) per Watt of power.
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CIDDRAM Mixed-Signal Parallel Distributed Array Processor
AbscrocrWe present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 x 128 vector-matrix multiplier on a single 3 mm x 3 mm ch...
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